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Silicon Packaging Design Engineer
Intel     Phoenix, AZ 85067
 Posted 11 days    

**Job Description**

Seeking highly motivated candidate to a part of an exciting and challenging environment in the Data Center and Artificial intelligence group. Selected candidate will support development for substrate design from concept through tape out, implementing physical layout and routing of the package (substrate) design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works in a co-design environment with other groups such as silicon, Board, Power and signal integrity teams to optimize performance and pinout. Ensures compliance to substrate design rules while contributing to internal and external reviews. Initiates manufacturing and assembly documentation/collateral into the product lifecycle management system of record.The Data Center and Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies-spanning software, processors, storage, I/O, and networking solutions-that fuel cloud, communications, enterprise, and government data centers around the world.

Behavioral traits

+ Proven track record of collaboration and teamwork to deliver results.

+ Verbal communication, technical writing, and presentation skills

+ Independent research, debugging, and troubleshooting capabilities.

**Qualifications**

Minimum Qualifications:

+ Bachelor of Science degree in Electrical, Computer, Mechanical engineering.

+ 1+ year experience/exposure in physical/electrical design relevant to semiconductor packaging or PCB

+ 1+ year experience/exposure to design and/or modeling software tools Additional

Preferred Qualifications:

+ Experience with high-speed layout techniques that involved parallel and serial differential interfaces.

+ Experience in Package/Substrate technology development.

**Inside this Business Group**

The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

**Other Locations**

US, OR, Hillsboro; US, CA, Santa Clara

**Posting Statement**

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits**

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Annual Salary Range for jobs which could be performed in US, California: $83,077.00-$124,371.00

*Salary range dependent on a number of factors including location and experience

**Working Model**

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. **In certain circumstances the work model may change to accommodate business needs.**

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Job Details


Employment Type

Full Time

Number of openings

N/A


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